High stresses in semiconductor die and other packaging elements can be developed in electronic assemblies subjected to extremely low ambient temperatures leading to reliability concerns. In this work, we have characterized and modeled the silicon die stresses occurring in flip chip assemblies at low temperatures. Stress measurements have been made at temperatures down to −180°C using test chips incorporating piezoresistive sensor rosettes. The obtained stress measurement data have been correlated with the predictions of nonlinear finite element models. A microtester has been used to characterize the stress-strain behavior of the solders and encapsulants from −180 to +150°C to aid in this modeling effort.

This content is only available via PDF.
You do not currently have access to this content.