Abstract
High speed computation is driving VLSI custom chips into smaller micron sizes and scale down power supplies. To accomplish very high speed, industry is developing shut down methods and short channel devices. Going below 0.5 micron technology speed is accomplished but hot spots, power density, and die failure are increased. Failure accumulated knowledge has not yet established a classic theory. In this paper, the STEPS method is used to determine the power dissipation in a CMOS circuit The experiment demonstrates dynamic power dissipation and assumes that static power dissipation is negligible in the CMOS devices. Each node is examined individually as signals are propagated through the chip. At each node the power distribution in the form of heat is determined.
